As the number of electronic elements contained on semiconductor integrated circuits continues to increase, the problems of reducing and eliminating defects in the elements becomes more difficult. To achieve higher population capacities, circuit designers strive to reduce the size of the individual elements to maximize available die real estate. The reduced size, however, makes these elements increasingly susceptible to defects caused by material impurities during fabrication. These defects can be identified upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective circuits is economically undesirable, particularly if only a small number of elements are actually defective.
Therefore, typically redundant elements are provided on the circuit to reduce the amount of semiconductor scrap. If a primary element is determined to be defective, a redundant element can be substituted for the defective element. Substantial reductions in scrap can be achieved by using redundant elements.
One type of integrated circuit device which uses redundant elements is electronic memory. Typical memory circuits comprise millions of equivalent memory cells arranged in addressable rows and columns. By providing redundant elements, either as rows or columns, defective primary rows or columns can be replaced. Thus, using redundant elements reduces scrap without substantially increasing the cost of the memory circuit.
There are limitations inherent in this approach that affect yield and downstream costs. Although earlier generations of memory devices could compensate by supplying a few redundant rows and columns, new generations of memory devices require considerably more redundant memory to compensate for multiple failed sections.
Thus, semiconductor memory manufacturers are faced with the problem of maximizing repairabilty of semiconductor memory to maximize yield with minimum impact on production costs, and without adding considerable complexity to the semiconductor memory architecture. Moreover, the increase in yield has to be achieved without significantly increasing overall cost of the memory system, and the size of the memory package.
Many manufacturers have attempted to achieve these goals by combining partially defective chips, or "partials," into packages which have non-standard configurations. However, the partials must be carefully matched to ensure there are no "holes" in the addressing space of the finished device. Furthermore, the addressing schemes which are employed to map the partials into a contiguous addressing space are different from those used when replacing defective rows and columns with spare elements, thus increasing the complexity of the programming which the manufacturer must incorporate into its fabrication process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a simple, and yet effective way to enhance the usability of defective semiconductor memory to maximize yield, but with minimum impact on production costs and without adding considerable complexity to the semiconductor memory architecture.